The high-performance motor drive chip FU6866 incorporates ME (Motor Engine) core and 8051 core. ME core integrates FOC, MDU, LPF, PID and SVPWM modules that allow for automatic calculation of FOC or quare- ave control by the hardware for sensored/sensorless BLDC/PMSM motors. 8051 core is used for parameter configuration and routine processing. Most of 8051 core instruction cycles takes 1T or 2T clock cycle(s).
The dual cores work in parallel to achieve high-performance motor control. The FU6866 integrates high-speed operational amplifiers, comparators, high-speed ADC, CRC, SPI, I2C, ART, LIN, CAN, Timers and built-in LDO, which are suitable for FOC or square-wave based BLDC/PMSM motors.
Build-in 180V gate driver for 6 N-Channel MOSFETs.
| P/N: | FU6866 Q | FU6866 Q1 | |
| Package | QFN56 7×7 | QFN56 7×7 | |
| Motion Engine ME | x | x | |
| FOC Hardware | x | x | |
| SVPWM Hardware | x | x | |
| BLDC Hardware | x | x | |
| Single Phase | – | – | |
| PI/PID | 4 | 4 | |
| LPF | 4 | 4 | |
| MDU | 4 | 4 | |
| Sin/Cos/Atan | 4 | 4 | |
| PFC Hardware | – | – | |
| MCU core | 8051 | 8051 | |
| MIPS [MHz] | 24 | 24 | |
| Flash [kB] | 32 | 32 | |
| RAM [kB] | 4 | 4 | |
| GPIO | 36 | 36 | |
| I²C | 1 | 1 | |
| UART | 2 | 2 | |
| SPI | 1 | 1 | |
| CAN | 1 | 1 | |
| LIN | 1 | 1 | |
| DMA | 2 | 2 | |
| Timer | 6 | 6 | |
| WDT | 1 | 1 | |
| PreDriver | 6N | 6N | |
| Driver Voltage, max. [V] | 180 | 180 | |
| Drive Current, max. + [A] | 0,9 | 0,9 | |
| Drive Current, max. – [A] | 1,1 | 1,1 | |
| Sensor/Sensorless Square Wave | x | x | |
| Sensor SVPWM | x | x | |
| Sensor FOC | x | x | |
| Sensorless FOC | x | x | |
| ADC | 1 | 1 | |
| ADC channels | 16 | 16 | |
| ADC resolution [bit] | 12 | 12 | |
| DAC | 2 | 2 | |
| DAC resolution [bit] | 9/6 | 9/6 | |
| OP | 4 | 4 | |
| Comparator | 3 | 3 | |
| Temp. Range (6,5-28V) | -40…85°C | – | |
| Temp. Range (6,5-18V) | – | -40…125°C | |
| AEC-Q100 | – | Grade 1 |
